This invention relates to the field of digital systems and more particularly to devices for implementing digital systems.
The advent of Very Large Scale Integrated (VLSI) circuit technology offers new opportunities and poses new design problems to the computer architect. This technology promises a substantial reduction in the cost of high volume components, such as microprocessors. However, the promised economics may not be achieved in larger computers using conventional design techniques since the time and the cost involved in designing a particular VLSI chip using conventional techniques is very high (e.g., one year and a 100,000 dollars is not uncommon) and the number of each VLSI component needed in the production of such computers may be relatively small, making unit cost very high. Consequently, a universal VLSI chip that can be specialized to implement various digital sub-systems is very desirable, especially if the specialization can be done in a manner similar to conventional ROM programming.
The prior art approaches to utilizing VLSI technology are exemplified by developments in programmable logic array (PLA) circuitry. The traditional PLA is a combinational circuit which produces multiple Boolean outputs from its inputs. It differs from a read-only memory (ROM) only in that implicants of Boolean functions are stored rather than the minterms, so that it is not necessary to have a word of storage for every input combination. It is usually implemented in the form of two arrays: an "AND" array which forms selected conjunction signals (implicants) based on input data, and an "OR" array which combines conjunction signals to form the correct outputs. The array is programmed by selecting (via make-break connections) whether a conjunction line is gated by a 1, 0, or neither on each input, and whether an output line responds to a conjunction line or not. These may be viewed as diode connections, as in a ROM.
In most computer designs, there is little opportunity to use PLA's because it is rare to have several signals which are complex functions of the same small set of input signals, and most cases that do occur are implementable with ROM's. Large size combinational PLA's are not useable, due to pin limitations constraining the number of inputs available. In response to pin limitations, some PLA's have added flip-flops on the chip, to provide feedback from outputs back to inputs in classic state-machine style. While these PLA's can be used in a much wider range of applications, they suffer from having too few flip-flops and from inefficient utilization of the logic potential in the AND and OR arrays. U.S. Pat. Nos. 3,816,725, 3,818,452 and 3,849,638 to D. L. Greer exemplify prior art approaches to the use of PLA.
It is an object of the present invention to provide a universal logic element for digital systems.
It is another object to provide a logic array for implementing multiple output, combinational and sequential, synchronous and asynchronous networks.
It is yet another object to provide a logic array which may be split into multiple sections for performing independent functions.
It is a further object to provide a universal logic array which is programmable.
Still another object is to provide a programmable logic array which is densely packed with respect to functions.